A power amplifier employing an emitter grounded bipolar transistor indispensably requires a base bias circuit which operates in a manner close to a regulated voltage source. A regulated voltage source is more suitable for a bias circuit than a regulated current source for reasons set forth below.
Consider that an RF input is applied to an emitter grounded bipolar transistor which is applied with a bias at a base from a regulated voltage source. When input power is sufficiently small, this emitter grounded bipolar transistor presents a small-signal operation, so that its collector current is substantially equal to a so-called collector bias current which flows when no signal is supplied to an amplifier.
Contrary to the above, as the input power is gradually increased, the collector current of the emitter grounded bipolar transistor increases to a current several times or more larger than the collector bias current. This increase in the collector current realizes higher saturation output and low distortions.
On the other hand, when a bias is applied to the base from a regulated current source, the collector current is maintained to be hFE times as large as the base bias current at all times, so that the collector current will not be increased even if the input power is increased. Therefore, when the collector bias current is set equivalent to the base bias applied by a regulated voltage source, gain compression, experienced in large-current operations, occurs at lower input power. In other words, the saturation characteristic is degraded to cause a reduction in power added efficiency and a degradation in linearity.
Also, when the collector bias current is set equivalent to a collector current when a base bias is applied by a regulated voltage source and when the input power is large, a collector current flows even when no RF signal is supplied and the input power is small, thus giving rise to a problem of increased power consumption and the like.
For the foregoing reasons, a power amplifier employing an emitter grounded bipolar transistor indispensably requires a base bias circuit which operates in a manner close to a regulated voltage source. As a conventional example of the base bias circuit which operates in a manner close to a regulated voltage source, there is a first conventional amplifier described in Japanese Patent No. 3377675. This is illustrated in FIG. 1. The operation of this circuit will be described in accordance with an embodiment of Japanese Patent No. 3377675.
FIG. 1 (see FIG. 1 in Japanese Patent No. 3377675) is a circuit diagram of the first conventional amplifier of Japanese Patent No. 3377675, FIG. 2 (see FIG. 2 in Japanese Patent No. 3377675) is a graph showing a voltage applied to the base of a transistor and to a diode in the circuit illustrated in FIG. 1, and FIG. 3 (see FIG. 3 in Japanese Patent No. 3377675) is a graph showing input/out When an emitter grounded amplifier comprising a bipolar transistor is used as a linear amplifier, to provide an applied voltage at B1 point on the base side, a voltage applied from external voltage source VB is converted to an arbitrary voltage value, for example, through a resistor division using resistors R1 and R2, and then diode D1 is inserted between B2 point and B1 point in the figure such that B1 point opposes a cathode terminal of the diode, as illustrated in FIG. 1.put characteristics of the circuit of FIG. 1. Simultaneously, a capacitor C1 is inserted between B2 point and a ground potential, such that the resulting impedance value is sufficiently small as compared with an impedance when a bias resistor side is viewed from B2 point.
When the operation point of emitter grounded transistor Tr1 in FIG. 1 is set in an A-class region, transistor Tr1 is in a linear operation state to present constant phase excursions for both gain and input/output power when the input power has a sufficiently small voltage as indicated by V1 in FIG. 5 (see FIG. 9 in Japanese Patent No. 3377675), and when the input power has a voltage amplitude which does not exceed a potential difference between bias voltage VB1 applied to B1 point and ON voltage Vth of the base-emitter diode. However, when voltage amplitude V2 at B1 point increases, as the input power increases, and exceeds the potential difference between bias voltage VB1 applied to the aforementioned B1 point and ON voltage Vth of the base-emitter diode, as indicated by V2 in FIG. 5, transistor Tr1 enters a non-linear operation state, and cannot maintain the operation point as the A-class, so that the power gain gradually decreases. Also, when a voltage value at B1 point swings to a potential equal to or lower than ON voltage Vth of the base-emitter diode, an ON-state time and an OFF-state time occur between the base and emitter of the aforementioned transistor Tr1.
In the On state, the input impedance of the base-emitter diode is equal to that when the A-class operation point is maintained, whereas in the OFF state, the input impedance of the base-emitter diode is higher, as compared with that when the A-class operation point is maintained, causing the voltage value at B1 point to largely swing to the negative side in this event. When the A-class operation point is maintained, the voltage value at B1 point is constant at VB1, when averaged over time, whereas in the OFF state, the voltage value at B1 point is smaller than VB1, when averaged over time. A junction capacitance value of the base-emitter diode has voltage dependence. Therefore, fluctuations in a voltage applied between the base and emitter result in fluctuations in the junction capacitance of the base-emitter diode, so that the input impedance of the emitter grounded amplifier presents a value different from that when the input power is sufficiently small and the A-class operation is maintained.
On the other hand, the potential at B2 point is determined by a voltage value of the regulated voltage source and a division ratio of resistors R1, R2, and is not affected by an increase in the input power, so that if the potential at B1 point gradually becomes lower than that during the small-signal operation as mentioned above, a voltage value VBE2 applied across diode D1 shown in FIG. 1 gradually increases as shown in FIG. 2. Accordingly, the junction capacitance possessed by diode D1 within the bias circuit exhibits fluctuations reverse to fluctuations in the junction capacitance of the base-emitter diode of the aforementioned emitter grounded transistor Tr1. Therefore, as the input power gradually increases, the input power increases in amplitude, accompanied with fluctuations in the input impedance of emitter grounded transistor Tr1, however, the impedance of diode D1 fluctuates to cancel them out, thus making it possible to restrain fluctuations in the input impedance of emitter grounded transistor Tr1 and reduce a pass phase excursion as compared with the conventional circuit. Further, as an increase in the voltage value applied across diode D1 causes an increase in the value of a current which flows into the base of transistor Tr1 through diode D1, the collector current increases, making it possible to solve saturated output power at the collector terminal and to increase a reduction in the power gain as well.
However, as the input power becomes higher to cause an increase in the bias current flowing into diode D1, the voltage becomes lower due to a voltage drop caused by resistor R1, and even the potential at B2 point in FIG. 2 becomes lower, so that the circuit can no longer operate as a regulated voltage source. There is therefore a first problem that the current flowing through resistor R2 must be increased to such a degree that the current flowing into diode D1 can be neglected.
This first problem is alleviated by a second conventional amplifier of FIG. 4, which is described in FIG. 4 in the same Japanese Patent No. 3377675. In FIG. 4, bipolar transistor Tr2 is connected between B2 point of a base bias circuit for dividing supply voltage VB with resistors R1, R2 and the base of transistor Tr1 such that the base-emitter of transistor R2 is oriented in the forward direction, and supply voltage VC is applied to the collector of transistor Tr2. Capacitor C1 is inserted between point B2 in the base bias circuit, i.e., the base terminal of transistor Tr2, and a ground point to present an impedance sufficiently smaller than an impedance when bias resistors R1, R2 are viewed from the base.
This second conventional amplifier utilizes a PN junction between the base and emitter of transistor Tr2, in contrast to that which utilizes a PN junction of diode D1 arranged in the base bias circuit illustrated in FIG. 1, wherein the operation of the circuit is substantially the same as the first conventional amplifier in which diode D1 is arranged in the base bias circuit, as illustrated in FIG. 1. However, since the aforementioned transistor Tr2 forms an amplifier circuit, the base bias current is amplified by this transistor Tr2, and is supplied to the base of emitter grounded transistor Tr1. It is therefore possible to reduce the current which flows into the base bias circuit, composed of the aforementioned resistors R1, R2, for generating the original base bias.
Though reduced, however, the second conventional amplifier is similar to the first conventional amplifier in that it suffers from the first problem that the current flowing through resistor R2 must be increased to such a degree that the current flowing into the base of transistor Tr2 can be neglected. Further, since the emitter grounded bipolar transistor exhibits an extremely high mutual conductance, the base must be applied with a strictly regulated voltage. However, in the first and second bias circuits, which generate this voltage through resistance division using resistors R1, R2, a second problem arises in that they are strongly affected by fluctuations in voltage between the base and emitter due to the temperature, variations attributable to the manufacturing, and the like.
It is a third conventional amplifier described in JP-A-2002-9559 that alleviates the first and second problems. FIG. 6 (see FIG. 5 in JP-A-2002-9559) illustrates a circuit diagram of the third conventional amplifier. In the third conventional amplifier, resistor 18 is not directly grounded, but is grounded through a reference voltage circuit composed of bipolar transistor Tr19 and bipolar transistor Tr20. The potential at a base of bipolar transistor Tr19 is equal to the sum of VBE of bipolar transistor Tr20 and VBE of bipolar transistor Tr19.
This circuit is designed such that the collector current density of bipolar transistor Tr20 is equal to the collector current density of power transistor Tr22. Therefore, VBE of power transistor Tr20 is equal to VBE of power transistor Tr22.
A base current of power transistor Tr22 is set equal to an emitter current of bipolar transistor Tr21; a base current of bipolar transistor Tr20 is set equal to an emitter current of bipolar transistor Tr19; an emitter area of bipolar transistor Tr20 is set equal to that of bipolar transistor Tr19; and an emitter area of power transistor Tr22 is set larger than that of bipolar transistor Tr21. Accordingly, VBE of bipolar transistor Tr21 is higher than VBE of bipolar transistor Tr19. The voltage drop of resistor 18 is equal to the difference between VBE of bipolar transistor Tr21 and VBE of bipolar transistor Tr19.
Assuming herein that DC current amplification ratios of the transistors are all equal to β for simplicity,
[Equation 1]
                              IC                      Tr            ⁢                                                  ⁢            22                          =                                            β              2                        ·                          IB                              Tr                ⁢                                                                  ⁢                21                                              =                                    β              2                        ·                          {                                                I                  ref                                -                                                      IC                                          Tr                      ⁢                                                                                          ⁢                      20                                                        ⁡                                      (                                          1                      +                                              1                                                  β                          2                                                                                      )                                                              }                                                          (        1        )            
Here, from the fact that the amplifier is designed such that the collector current density of bipolar transistor Tr20 is equal to the collector current density of power transistor Tr22, the relationship between ICTr22 and ICTr20 is equal to the relationship between power transistor Tr22 and bipolar transistor Tr20 in regard to the area ratio. When S22 designates the area of power transistor Tr22, and S20 the area of bipolar transistor Tr20,
[Equation 2]
                              IC                      Tr            ⁢                                                  ⁢            22                          =                              1                                          1                                  β                  2                                            +                                                                    S                    22                                                        S                    20                                                  ⁢                                  (                                      1                    +                                          1                                              β                        2                                                                              )                                                              ·                      I            ref                                              (        2        )            When β2>>1, the circuit serves as a current source with ICTr22≈(S22/S20)Iref.
This circuit can alleviate the aforementioned second problem because changes in VBE's due to the temperature and variations attributable to the manufacturing cancel each other out. Also, in regard to the aforementioned first problem, the circuit can operate in a manner close to a regulated voltage source because a reduction in VBE of power transistor Tr22 does not affect VBE of bipolar transistor Tr20, and they do not cancel each other out.
Here, Iref is given by:
[Equation 3]
                              I          ref                =                              VB            -                          VBE                              Tr                ⁢                                                                  ⁢                21                                      -                          VBE                              Tr                ⁢                                                                  ⁢                22                                                          RI            ⁢                                                  ⁢            7                                              (        3        )            and is therefore affected by fluctuations in VBE.
However, the bias circuit of the second conventional amplifier illustrated in FIG. 4 has the first problem that the current flowing through resistor R2 must be increased to such a degree that the current flowing into the base of transistor Tr2 can be neglected, whereas in the bias circuit of the third conventional amplifier in FIG. 6, since the value of Iref can be reduced if a large area ratio is selected, the value of R17 can be increased to keep fluctuations small.
The foregoing consideration has been made in regard to an amplifying transistor biased to A-class in accordance with an embodiment of Japanese Patent No. 3377675. In the following, a description will be given of those conventional amplifiers when they are biased to B-class or to AB-class close to B-class. In CDMA portable telephone terminals such as W-CDMA, output power is controlled in excess of 50 dB in order to avoid a near-far problem (problem that communications cannot be made with a remote terminal due to the influence of radiowaves from neighboring terminals). Therefore, communications are made with low power at an increased frequency in a region where a large number of base stations are installed. The ratio of power consumption to the output power in low-power transmission is lower as the operation of an amplifier is brought closer to B-class from A-class. In other words, a higher power added efficiency is provided as the amplifier is operated in a state closer to B-class.
Consider now a case in which an emitter grounded amplifier circuit which operates in a manner close to B-class is biased by the aforementioned bias circuit of the first to third conventional amplifier which operates in a manner close to a regulated voltage source. The emitter grounded amplifier circuit, which is biased in a state close to B-class, causes a gain expansion, as shown in FIG. 7, because the base current increases with the input power increasing, due to the rectifying action of the base-emitter diode.
The gain fluctuates when this amplifier having the gain expansion characteristic is applied with a broadband modulated signal associated with a change in power, such as a W-CDMA signal, wherein a third problem arises in that the fluctuations in the gain cause a signal distortion. As shown in FIG. 8, this signal distortion appears to be interfering waves to adjacent channels next to a communications channel. The ratio of a signal strength on the communications channel to the strength of the interfering waves to the adjacent channels is called “adjacent channel power ratio” (ACPR).
As conventional examples for solving the third problem, there are distortion canceling approaches as proposed in JP-A-2000-183663, JP-A-2002-111400, JP-A-2002-171145, and JP-A-10-135750. These approaches has a point common to them in that, as opposed an amplification stage having a gain expansion characteristic shown at a second amplification stage, another amplification stage shown at a first amplification stage is designed to have a gain compression characteristic, thereby canceling out gain fluctuations of the two parties to reduce distortions, as illustrated in FIG. 9. In the following, a description will be given of the cancellation of distortions with the gain expansion amplification stage and gain compression amplification stage.
The amplification characteristic of an arbitrary amplifier is Taylor expanded as shown below:
[Equation 4]
                              V          out                =                              ∑            n                                                          ⁢                                          ⁢                                    a              n                        ⁢                          V              in              n                                                          (        4        )            
When this amplifier is applied with two sinusoidal waves given by:[Equation 5]Vin=A(sin ω1t+sin ω2t)  (5)changes occur in the main signal and the distortion component due to the non-linearity of the amplifier.
When (5) is substituted into (4), and Equation (4) is calculated until n=5, a component at a frequency ω1 of Vout is given by:
[Equation 6]
                                          V            out                    ⁢                      ❘                          ω              1                                      =                              (                                                            a                  1                                ⁢                A                            +                                                9                  4                                ⁢                                  a                  3                                ⁢                                  A                  3                                            +                                                25                  4                                ⁢                                  a                  5                                ⁢                                  A                  5                                                      )                    ⁢          sin          ⁢                                          ⁢                      ω            1                    ⁢          t                                    (        6        )            
Among coefficients of sin, a1A represents an amplification ratio (i.e., gain), and the others represent fluctuations in the gain with respect to an input amplitude (i.e., whether gain expansion or gain compression). Also, a frequency component 2ω1-ω2 of Vout is given by:
[Equation 7]
                                          V            out                    ⁢                      ❘                          (                                                2                  ⁢                                      ω                    1                                                  -                                  ω                  2                                            )                                      =                              (                                                            3                  4                                ⁢                                  a                  3                                ⁢                                  A                  3                                            +                                                25                  8                                ⁢                                  a                  5                                ⁢                                  A                  5                                                      )                    ⁢          sin          ⁢                                          ⁢                      (                                          2                ⁢                                  ω                  1                                            -                              ω                2                                      )                    ⁢          t                                    (        7        )            
(7) expresses a third inter-modulation distortion (IM3) component of Vout. Here, when a1, a3, a5 have the same sign, (6) shows the gain expansion characteristic, where the gain increases together with input amplitude A over a wide range of A. Also, under the same condition, sin in (7) has the same coefficients as those of sin in (6). Defined this way, a basic wave matches IM3 in phase.
Generally, the phase cannot be defined regarding signals having a different frequency, but in this event, the signal shown in (5) is used for the input, two waves spaced by frequency (ω2-ω1)/2π from each other match in phase every 2π/(ω2-ω1) seconds. In the same way, since the basic wave and IM3 spaced by (ω2-ω1)/2π from each other have the same phase angle every 2π/(ω2-ω1) seconds, they are defined by terms “in-phase” and “opposite phase.” (6), (7) show that the basic wave and IM3 match in phase when the gain expansion prevails in a wide range of input power.
Here, a distortion canceling phenomenon occurs if the phase of IM3 generated by amplifying distortions of the preceding stage at the subsequent stage differs by ±90 degrees from the phase of IM3 generated by amplifying the basic wave at the subsequent stage. As such, in the following, the phase angle within ±90 degrees between the basic wave and IM3 is expressed by “in phase,” and the phase angle larger than ±90 degrees is expressed by “in opposite phase” for simplicity.
FIG. 10 shows, as an example, the relationship of the phase between the basic wave and IM3 signal when the third conventional amplifier illustrated in FIG. 6 is biased to AB-class close to B-class for analysis. Here, the magnitude of the IM3 signal is enlarged by a factor of ten for purposes of illustration because it is small as compared with the basic wave. The absolute value of the phase does not have meaning in particular because it simply represents a delay of input/output. FIG. 11 in turn shows the appearance of the gain expansion in that event.
An input power range drawn in FIG. 10 is indicated by arrows in FIG. 11. In many cases, the basic wave is in phase with IM3 in amplifiers which exhibit the gain expansion characteristic. FIG. 13 shows an exemplary relationship of the phase between the basic wave and IM3 signal when an analysis is made employing a gain expansion amplifier which uses a gain variable amplifier and a multiplier in FIG. 12. Here, the magnitude of IM3 is again enlarged by a factor of ten for purposes of illustration. As shown, the basic wave is in phase with IM3. Also, FIG. 14 shows the appearance of the gain expansion in that event. FIG. 14 shows the gain expansion characteristic.
Conversely, in many cases, the basic wave is in opposite phase to IM3 in amplifiers which exhibit the gain compression characteristic. As is the case with the gain expansion amplifier, FIG. 15 shows an exemplary phase relationship between the basic wave and IM3 signal when an analysis is made employing a gain expansion amplifier which uses the variable gain amplifier (used with the reversed control characteristic of a gain control terminal) and multiplier in FIG. 12. Here, the magnitude of IM3 is again enlarged by a factor of ten for purposes of illustration. As shown, the basic wave is in opposite phase to IM3. Also, FIG. 16 shows the appearance of gain expansion. FIG. 16 shows the gain compression characteristic.
Specifically, distortions can be reduced by a combination of the gain expansion amplification stage with the gain compression amplification stage because the phase angles of the basic wave and IM3 are inverted at respective stages, so that IM3, generated at the preceding stage and amplified at the subsequent stage, has a phase opposite to IM3 generated by amplifying the basic wave at the subsequent stage to cancel them out.
The respective conventional examples attempt to reduce distortions in the following manner. First, in the conventional example described in JP-A-2000-183663, a gate bias to an FET amplifier circuit is set to B-class to have the gain expansion characteristic at a first amplification stage illustrated in FIG. 9, while a gate bias to an FET amplifier circuit is set to AB-class to have the gain compression characteristic at a second amplification stage, thereby canceling out the gain expansion characteristic and gain compression characteristic so as to reduce distortions.
Next, in the conventional example described in JP-A-2002-111400, a base bias to an HBT amplifier circuit is set to AB-class to have the gain expansion characteristic at the first amplification stage in FIG. 9, while a gate bias to an HBT amplifier circuit is set to A-class to have the gain compression characteristic at the second amplification stage, thereby canceling out the gain expansion characteristic and gain compression characteristic so as to reduce distortions.
Then, in the conventional example described in JP-A-2002-171145, a gate bias to an MES amplifier circuit is set to A-class to have the gain compression characteristic at the first amplifier stage in FIG. 9, while a gate bias to a MOS amplifier circuit is set to AB-class to have the gain expansion characteristic at the second amplification stage, thereby canceling out the gain expansion characteristic and gain compression characteristic so as to reduce distortions.
Finally, in the conventional example described in JP-A-10-135750, a base bias to an HBT amplifier circuit is set to AB-class or C-class to have the gain expansion characteristic at the first amplification stage in FIG. 9, while a gate bias to an HBT amplifier is set to A-class to have the gain compression characteristic at the second amplification stage, thereby canceling out the gain expansion characteristic and gain compression characteristic so as to reduce distortions.
For simplicity, these conventional examples are collectively called the “fourth conventional amplifiers.” These fourth conventional amplifiers combine the gain expansion amplification stage with the gain compression amplification stage to reduce distortions, and therefore have a fourth problem of the inability to apply an amplifier that exhibits the gain expansion characteristic with good power added efficiency at low output to all amplification stages.
In addition, as conventional examples which attempt to reduce distortions by canceling out phase-rotated distortion components, there is a differential frequency injection technique, as proposed by Japanese Patent No. 3337766, and JP-A-2003-338713.
FIG. 17 is an explanatory diagram for distortion compensation through second-order distortion (differential frequency) injection, shown in FIG. 9 of Japanese Patent No. 3337766. By injecting a differential frequency into a non-linear element, phase-rotated distortion components are canceled out.
Assuming in (4) that an input signal is given by the sum of two sinusoidal waves and a differential frequency therebetween as given by:[Equation 8]Vin=A(sin ω1t+sin ω2t+D cos(ω2−ω1)t)  (8)(8) is substituted into (4), and Equation (4) is calculated until n=5. Then, a component of a basic wave (ω1) of Vout resulting from the non-linearity of the amplifier is given by:[Equation 9]
                                          V            out                    ⁢                      ❘                          ω              1                                      =                              {                                                            a                  1                                ⁢                A                            +                                                9                  4                                ⁢                                  a                  3                                ⁢                                                      A                    3                                    ⁡                                      (                                          1                      +                                                                        2                          3                                                ⁢                                                  D                          2                                                                                      )                                                              +                                                25                  4                                ⁢                                  a                  5                                ⁢                                                      A                    5                                    ⁡                                      (                                          1                      +                                                                        105                          8                                                ⁢                                                  D                          2                                                                    +                                                                        15                          8                                                ⁢                                                  D                          4                                                                                      )                                                              +                                                a                  2                                ⁢                                  A                  2                                ⁢                D                            +                                                a                  4                                ⁢                                                      A                    4                                    ⁡                                      (                                                                  6                        ⁢                        D                                            +                                                                        3                          2                                                ⁢                                                  D                          3                                                                                      )                                                                        }                    ⁢          sin          ⁢                                          ⁢                      ω            1                    ⁢          t                                    (        9        )            
Also, an IM3(2ω1−ω2) component of Vout is given by:
[Equation 10]
                                          V            out                    ⁢                      ❘                          (                                                2                  ⁢                                      ω                    1                                                  -                                  ω                  2                                            )                                      =                              {                                                            3                  4                                ⁢                                  a                  3                                ⁢                                                      A                    3                                    ⁡                                      (                                          1                      +                                              D                        2                                                              )                                                              +                                                25                  8                                ⁢                                  a                  5                                ⁢                                                      A                    5                                    ⁡                                      (                                          1                      +                                              3                        ⁢                                                  D                          2                                                                    +                                                                        2                          5                                                ⁢                                                  D                          4                                                                                      )                                                              +                              16                ⁢                                  a                  2                                ⁢                                  A                  2                                            +                                                1                  2                                ⁢                                  a                  4                                ⁢                                                      A                    4                                    ⁡                                      (                                                                  9                        ⁢                        D                                            +                                              3                        ⁢                                                  D                          3                                                                                      )                                                                        }                    ×          sin          ⁢                                          ⁢                      (                                          2                ⁢                                  ω                  1                                            -                              ω                2                                      )                    ⁢          t                                    (        10        )            
It can therefore be understood that an IM3 component shown in Equation 10 can be reduced in certain input amplitude A by selecting injection amount D to be a (negative) proper value. However, since injection amount D cannot be selected to reduce IM3 independently of the value of input amplitude A, it is necessary to optimize the injection amount by any method such as feed-back, feed-forward or the like.
For simplicity, the conventional examples of Japanese Patent No. 3337766 and JP-A-2003-338713 are collectively called the “fifth conventional amplifiers.” The fifth conventional amplifiers have a fifth problem that the injection amount must be adjusted by feed-back, feed-forward or the like because the optimal injection amount depends on the input amplitude.
In summarizing the foregoing, the prior arts have the following problems.
As the third problem mentioned above, the first to third conventional amplifiers have a drawback in which signals are distorted due to the gain expansion when they are used as biased in a state close to B-class in order to increase the power added efficiency at low output.
Also, as the fourth problem mentioned above, the fourth conventional amplifier has a drawback of the inability to employ the amplification stage, which exhibits a good power added efficiency at low output, at all stages due to the third problem mentioned above.
Then, as the fifth problem mentioned above, the fifth conventional amplifier has a drawback that there is a requirement for adjustment of the injection amount through feed-back, feed-forward or the like in the injection of a differential frequency signal due to the dependence of an optimal injection amount on the input amplitude.